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New grayscale technique opens a third dimension for nanoscale lithography

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Posted August 30, 2013
New grayscale technique opens a third dimension for nanoscale lithography

New grayscale technique opens a third dimension for nanoscale lithography
Scanning electron micrograph (SEM) showing a top-view along with an SEM (inset) showing a cross-sectional view of grayscale structures fabricated using a combination of e-beam lithography, photolithography, and resist spray coating. The superimposed schematic illustrates e-beam direct writing of nanoscale vertical staircases (SEM inset) on a substrate with microscale grayscale topography. The initial grayscale patterns were generated on a laserwriter. After reactive ion beam etching, the patterns were simultaneously written into 2 µm, 0.5 µm, and 30 µm deep features.

Engineers at the NIST Center for Nanoscale Science and Technology (CNST) have developed a new technique for fabricating high aspect ratio three-dimensional (3D) nanostructures over large device areas using a combination of electron beam (e-beam) lithography, photolithography, and resist spray coating. While it has long been possible to make complicated 3D structures with many mask layers or expensive grayscale masks, the new technique enables researchers to etch trenches and other high aspect ratio structures with nanometer scale features without using masks and in only two process stages.

The fabrication of 3D semiconductor and dielectric structures that are patterned by exposing resist with varying intensity grayscale gradients has been essential to a broad range of applications such as digital lenses, micro-electromechanical systems, and fluidic medical devices.

Unlike devices that rely on conventional masks, which have areas that simply transmit or block light to form a pattern, the fabrication of these devices has typically relied on 3D grayscale masks which have varying levels of transparency and depend on the use of proprietary materials. Because the chemistry is proprietary and because the masks are prepared using complicated processes best suited to small surface areas, they are often prohibitively expensive. The next generation of these devices requires lower costs, larger surface areas, and ever-smaller feature sizes.

Read more at: Phys.org

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