Greater numbers of ever-smaller components are required to fit on computer chips to meet the ongoing demands of miniaturizing electronic devices. Consequently, computer chips are becoming increasingly crowded. Designers of electronic architectures have therefore followed the lead of urban planners and started to build upward. In so-called ‘three-dimensional (3D) packages’, for example, several flat, two-dimensional chips can be stacked on top of each other using vertical joints.
Controlling the properties of these complex structures is no easy task, as many factors come into play during production. Faxing Che and Hongyu Li and co-workers from the A*STAR Institute of Microelectronics, Singapore, have now developed a powerful modeling method that allows large-scale simulations—and optimization—of the fabrication process, which provides welcome assistance to designers. Among the challenges of producing tightly packed computer chips is the need to prevent warpage of the underlying silicon wafer as electronics components are stacked on it (see image). Warpage leads to a number of unwanted effects. “Strong warpage can cause wafer breakage, it makes tight packing more difficult and some processing machines cannot handle high-warpage wafers,” explains Li. The degree of warpage depends on many design and process parameters, and optimizing the procedure experimentally is time-consuming and costly.
Read more at: Phys.org